The present disclosure relates to methods for processing microelectronic workpieces, and in particular, methods for creating patterned structures on the microelectronic workpieces.
Semiconductor device formation involves a series of manufacturing techniques related to the formation, patterning and removal of a number of layers of material on a substrate. Over the last few decades, dimension shrinkage for device features has been the major driving force in the development of integrated circuit processing. By reducing the dimensions of feature sizes, substantial improvements have been achieved in reducing costs while boosting device performance. This reduction in feature size and related scalability, however, has created inevitable difficulties and complexities in manufacturing process flows especially with respect to patterning techniques used to achieve the reduced feature sizes.
Self-aligned multi-patterning (SAMP) techniques have been used to achieve reduced feature size in semiconductor processing beyond current photolithographic limits. For example, SAMP techniques have been used to achieve features sizes below 22 nanometers (nm) for Fin-Field-Effect-Transistor (FinFET) architectures. SAMP techniques use extra spacer formation and etch steps to achieve the pitch reduction needed to achieve these sub-22 nm structures. With respect to SAMP process flows, cores and spacers are two common hardmask materials that are used to obtain small feature sizes in advanced semiconductor processing techniques. For example, a conventional SAMP flow contains the following steps: core formation, spacer deposition, spacer etch, and core pull. In this approach, the final feature critical dimension (CD) is controlled by spacer deposition thickness and the physical features of the resulting spacer pattern. The spacer patterns are then transferred to underlying layers using further etch processes to form patterned structures.
At these small features size and particularly as feature sizes extend below 10 nm, roughness and uniformity controls for the deposition/etch processes used to form the spacer patterns and resulting pattern structures become extremely critical because roughness/uniformity variations can be a major source of process variations for such small dimension features. With the conventional SAMP techniques for these sub-10 nm nodes, for example, roughness has been found in patterned lines formed after pattern transfer of spacer patterns to underlying layers. These roughened patterned lines will carry undesired variations through subsequent process stages and eventually degrade the final features for the microelectronic workpiece being manufactured. Unlike direct patterning methods, improvement of line roughness is difficult and complicated due to the nature of SAMP techniques applied within complex process flows.
FIGS. 1A-D (Prior Art) provide example embodiments for a traditional process flow for a SAMP process that includes a core pull from spacers and a transfer of a spacer pattern to underlying layers.
Looking first to FIG. 1A (Prior Art), an example embodiment 110 for material layers and patterned structures is shown after lithography and etch processes (or prior SAMP processes) have been used to form cores 102 over underlying layers. For the example embodiment 110, the layers underneath the cores 102 include a hardmask layer 104 and a substrate 106, such as a semiconductor substrate for a microelectronic workpiece. Lithography processes can include optical lithography, extreme ultra-violet (EUV) lithography, and/or other desired lithography processes. Etch processes can include, for example, a reactive ion etching (RIE) process and/or other etch or strip processes that are used to form cores 102. The etch processes can include, for example, plasma etch processes having plasma gases containing fluorocarbons, oxygen, nitrogen, hydrogen, argon, and/or other gases under a variety of pressure and power conditions. In addition, this plasma etch can be done in multiple steps with different discharged plasmas for directionally etching to achieve the desired structures for cores 102.
It is noted that the cores 102 can include, for example, silicon, amorphous carbon, photoresist, and/or other materials. The hardmask layer 104 can be, for example, one or more of the following materials including but not limited to tetraethyl orthosilicate (TEOS), silicon oxide (SiOx), low temperature silicon oxide, silicon nitride (SiN), sacrificial SiN, SiCOH, silicon oxynitride (SiON), and/or other hardmask materials. The substrate 106 can be silicon and/or other substrate materials being used for the microelectronic workpiece.
FIG. 1B (Prior Art) provides an example embodiment 120 after a deposition process has been performed to deposit spacer layer 122 over the cores 102. The spacer layer 122, for example, can be silicon oxide, silicon nitride, metal oxide, metal nitride, and/or other protective spacer material. In one embodiment, the spacer layer 122 is deposited using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other deposition processes. It is also noted that the ALD method of deposition is the typically preferred deposition technique for SAMP spacers because it is based on self-limiting atomic layer deposition, which provides for atomically uniform film formation.
FIG. 1C (Prior Art) provides an example embodiment 130 after a spacer open process has been performed to form spacers 132 adjacent the cores 102, and a core pull process has been performed to pull the cores 102 and leave spacers 132 in a spacer pattern 134. The spacer open process can be, for example, an etch process that etches the spacer layer 122 to form the spacers 132 adjacent to the cores 102, and the core pull process can be an etch process that etches the cores 102 to leave the spacers 132. This etch process and the core pull process can also be plasma etch processes as described above with chemistry based upon the materials used for the cores 102 and the spacer layer 122. The spacer pattern 134 can be later transferred to underlying layers such as hardmask 104 and substrate 106.
FIG. 1D (Prior Art) provides an example embodiment 140 after a pattern transfer process has been performed to transfer the spacer pattern 134 to a patterned structure 142 within the underlying layers such as hardmask 104 and substrate 106. The pattern transfer process can be, for example, etch processes that etch the spacers 132, the hardmask 104, and/or the substrate 106 to form the patterned structure 142. Depending upon the etch processes used, a portion of the spacers 132 can be left as part of the patterned structure 142 transferred to the underlying layers from the spacer pattern 134. This etch processes for the pattern transfer can also be plasma etch processes as described above.
The resulting patterned structure 142 often includes pattern lines that extend longitudinally across the surface of the microelectronic workpiece being manufactured. As described above, traditional deposition/etch manufacturing processes lead to unacceptable roughness and/or non-uniformity in the pattern lines for small feature sizes such as features sizes below 22 nm and, more particularly, for features sizes below 10 nm.